The present invention relates to a data processing apparatus and method for multiplying floating point operands.
It is known to provide data processing systems with the ability to manipulate floating point numbers. The hardware mechanisms for performing floating point multiplication typically use the multiplier and multiplicand to generate numerous partial products. Various forms of carry-save adders are then used to reduce the partial products to two partial products. These final two partial products are then added before being rounded to produce the final product result.
A problem with the above is how to deal with subnormal results. Subnormal results are where the exponent value has the minimum permitted value and the significand (also referred to as a mantissa) is less than one, e.g. 0.001101. The nature of subnormal numbers is familiar to those in this technical field. One way of dealing with subnormal numbers is to treat them as exceptions and handle their processing in software. This is a low performance solution. If subnormal numbers are to be handled in hardware, then a problem is that the output of the adder from the two partial products is unlikely to be properly aligned for rounding. This requires that adder output to be shifted and then rounded using a further adder. The shifting and the further adder for the rounding introduce undesirable additional hardware and delay.
Commonly owned U.S. Pat. No. 8,463,834, the entire contents of which are hereby incorporated by reference, introduces an improved mechanism for multiplying floating point operands, whilst being able to deal with subnormal results, the mechanism described in that patent using an extra multiplication cycle to left or right shift the partial products before adding and rounding. By such an approach, it was then possible for the rounding constant to always be injected at a fixed location, thereby significantly simplifying the rounding process. However, whilst the approach does simplify the problem of dealing with rounding within subnormal results, it does require the use of an extra shift stage for the partial products, which can adversely affect performance.
It would hence be desirable to provide a mechanism that provided improved performance when multiplying floating point operands, whilst still enabling correct rounding for subnormal results.